With current demand for high density memory, die stacking technology is one solution to achieve a desired density. However, die stacking places many devices in parallel, which produces a capacitive loading effect that adversely reduces the bus bandwidth and limits the amount of data that can be transferred through a data link. There is a need for a viable solution that provides high density without reducing the maximum allowable data rate on a bus due to loading.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated, relative to other elements, for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements